Real-time FPGA-based human iris recognition embedded system: Zero-delay human iris feature extraction | |
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學年 | 101 |
學期 | 2 |
發表日期 | 2013-05-09 |
作品名稱 | Real-time FPGA-based human iris recognition embedded system: Zero-delay human iris feature extraction |
作品名稱(其他語言) | |
著者 | Amirshahram Hematian; Suriayati Chuprat; Azizah Abdul Manaf; Sepideh Yazdani; Nadia Parsazadeh |
作品所屬單位 | |
出版者 | |
會議名稱 | The 9th International Conference on Computing and Information Technology |
會議地點 | Bangkok, Thailand |
摘要 | Nowadays most of iris recognition algorithms are implemented based on sequential operations running on central processing units (CPUs). Conventional iris recognition systems use a frame grabber to capture a high quality image of an eye, and then system shall locate the pupil and iris boundaries, unwrap the iris image, and extract the iris image features. In this article we propose a prototype design based on pipeline architecture and combinational logic implemented on field-programmable gate array (FPGA). We achieved to speed up the iris recognition process by localizing the pupil and iris boundaries, unwrapping the iris image and extracting features of the iris image while image capturing was in progress. Consequently, live images from human eye can be processed continuously without any delay or lag. We conclude that iris recognition acceleration by pipeline architecture and combinational logic can be a complete success when it is implemented on low-cost FPGAs. |
關鍵字 | Biometrics;FPGA;Human Identification; Iris Recognition;Pattern Matching;Zero-Delay |
語言 | zh_TW |
收錄於 | |
會議性質 | 國內 |
校內研討會地點 | 無 |
研討會時間 | 20130509~20130510 |
通訊作者 | |
國別 | TWN |
公開徵稿 | |
出版型式 | |
出處 | Springer Berlin Heidelberg |
相關連結 |
機構典藏連結 ( http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/127038 ) |