Reconfigurable Double-Sampled Cascaded Sigma-Delta Modulator with Power Minimizing and System Stabilizing Strategy for Multi-Mode Applications
學年 109
學期 1
出版（發表）日期 2020-12-01
作品名稱 Reconfigurable Double-Sampled Cascaded Sigma-Delta Modulator with Power Minimizing and System Stabilizing Strategy for Multi-Mode Applications
作品名稱（其他語言）
著者 Hsin Liang Chen; Chi Hsiung Wang; Jen Shiun Chiang
單位
出版者
著錄名稱、卷期、頁數 Journal of Applied Science and Engineering, 23(4)
摘要 In this paper, a power minimizing strategy from a system- and circuit-perspective is developed for low-power reconfigurable multi-mode sigma-delta modulators. An experimental low-power modulator is designed for multi-mode systems with second- and fourth-order cascaded architectures. Several criteria are obtained to investigate the stability of the cascaded sigma-delta architecture. The proposed modulator can adapt to different system specifications with switchable stages and double-sampled techniques for better power efficiency. A test modulator chip is demonstrated with 0.13 μm CMOS technology. With the proposed strategy, the simulation results indicate that the designed fourth-order cascaded modulator will dissipate powers of 4.2, 11.3, and 20.2 mW and obtain a figure-of-merit (FoM) of 169, 149, and 157 at a supply voltage of 1.2 V for bandwidths 100kHz, 2 MHz, and 20 MHz, respectively.
關鍵字 Cascaded; Reconfigurable; Sigma delta modulator; Multi-mode
語言 en_US
ISSN 2708-9975
期刊性質 國外
收錄於 SCI Scopus
產學合作
通訊作者
審稿制度 否
國別 TWN
公開徵稿
出版型式 ,電子版
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